1. Technical Field
The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device and a method of fabricating the same.
2. Related Art
A kind and application field of electronic apparatuses have been increasing day by day and ultra-high integration, ultra-high speed, and ultra-low power of memory devices, which are embedded in a limited size to process large capacity of data with high speed, have been required.
A unit memory cell is generally configured to include a data storage region and a selection device configured to access the data storage region. A diode, a transistor, or the like is used as the selection device. The transistor has advantageous to reduce an operation voltage through control of a threshold voltage lower than the diode.
Further, through application of a vertical structure to the transistor, the transistor has received attention again as the selection device of the memory device.
FIGS. 1 to 4 illustrate cross-sectional views illustrating a method of fabricating a conventional semiconductor device, for example, a vertical transistor.
First, as illustrated in FIG. 1, a semiconductor substrate 101, 103 includes a common source region 101 and is patterned to form a pillar structure 103. At this time, an etching process is performed on the semiconductor substrate. Without an etch stop layer, it is difficult to etch different portions of the substrate at the same rate. Therefore pillar structures 103 may have different heights A1 and A2.
FIG. 2 illustrates a gate insulating layer 105 that is formed along a surface of the pillar structures 103.
FIG. 3 shows that a conductive material is deposited on the semiconductor substrate, including the gate insulating layer 105, and is then etched to form a gate electrode 107 on an outer wall of the pillar structure 103.
As illustrated in FIG. 4, the pillar structure is divided into a channel region 103A and a drain region 103B through an impurity ion implantation process. Interlayer insulating layers 109 are formed between the pillar structures 103.
However, as illustrated in FIG. 1, the semiconductor substrate may be non-uniformly etched, and thus, the pillar structures 103 may have different heights A1 and A2. As illustrated in FIG. 3, gate electrodes 107 may have different heights due to non-uniform etching during the formation of the gate electrode 107.
Therefore, when an impurity is ion implanted to a predetermined projection range (RP) to form drain regions 103B, overlapping lengths B1, B2, and B3 between the gate electrodes 107 and the drain regions 103B may become different from each other.
However, if transistors have drain regions with different overlapping lengths, then operation characteristics of the transistors become different. Thus, the reliability of the semiconductor device is graded.
As the size of semiconductor devices has decreased, structures having increasingly high aspect ratios are being etched. Therefore, there is a greater need for uniform etching.